1. Field of Invention
The present invention relates to a memory device, and more particularly, to a memory device for storage of both volatile data and non-volatile data.
2. Description of the Prior Art
Recently, along with increasing market demand for portable digital products, technologies and applications of flash memory have matured. These portable digital products include digital cameras, cellular phones, video game consoles, personal digital assistants, answering machines, and programmable ICs. Flash memory is a nonvolatile memory that stores data by changing a threshold voltage of a transistor storage unit to control a turn-on and turn-off of a conductive channel. This mechanism keeps the data stored in the memory from disappearing due to absence of power. Generally speaking, flash memory is recognized as a special structure of conventional electrically erasable and programmable read only memory (EEPROM).
FIG. 1 shows a structure diagram of a conventional flash memory 10. Flash memory 10 comprises a substrate 12, a source 14, a drain 16, a floating gate 18, and a control gate 20. The floating gate 18 and a channel 22 in the substrate 12 are isolated by an oxide layer 24, while the control gate 20 and the floating gate 18 are isolated by an oxide layer 25. The substrate 12 is connected to a reference voltage Vbb (conventionally, ground is used as the reference voltage). If the flash memory 10 is an N-type metal-oxide semiconductor (MOS) structure, then the substrate 12 is p-doped, and the source 14 and the drain 16 are n-doped. On the contrary, if the flash memory 10 is a P-type MOS structure, then the substrate 12 is n-doped, and the source 14 and the drain 16 are p-doped. Please note, for simplicity there is only one memory cell 26 shown in FIG. 1. In general, the flash memory 10 comprises multiple memory cells 26 arranged in an array and addressed by row and column for use as data storage.
The operation of the flash memory 10 is described in detail as follows. A control voltage Vcg inputted to the control gate 20 can change the amount of electrons stored on the floating gate 18, and further change the threshold voltage corresponding to the forming of the channel 22. Therefore, when reading data, the memory cell 26 distinguishes the two data statuses xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d by determining the amount of electrons stored on the floating gate 18. The two different data statuses are formed either by driving electrons in the channel 22 through the oxide layer 24 into the floating gate 18 to increase the amount of electrons stored in the floating gate 18, or by expelling the electrons stored in the floating gate 18, respectively. As a result, the threshold voltage is relatively high when there are more electrons stored in the floating gate 18, and the threshold voltage is relatively low when there are fewer electrons stored in the floating gate 18. In order to electrically connect the source 14 and the drain 16 of the memory cell 26, i.e. to form the channel 22, the control voltage Vcg is inputted to the control gate 20 to adjust the influence of the threshold voltage of the floating gate 18 at the channel 22. The data status (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) in the memory cell 26 under the external control voltage Vcg is determined by reading the current value flowing between the source 14 and the drain 16.
FIG. 2 shows a distribution plot of the threshold voltage of the memory cell 26 of FIG. 1. The distribution plot of FIG. 2 shows amount of the memory cells plotted against threshold voltage. For example, when a binary value xe2x80x9c1xe2x80x9d is to be stored in the memory cell 26, the memory cell 26 needs to be programmed such that the floating gate 18 will store more electrons and have a higher threshold voltage. For different memory cells 26, those which have xe2x80x9c1xe2x80x9d stored in them will not have the same threshold voltage, but will form a distribution like curve 28, more specifically they will have threshold voltages ranging from V11 to V12. On the contrary, when a binary value xe2x80x9c0xe2x80x9d is to be stored in the memory cell 26, the memory cell 26 needs to be erased such that that floating gate 18 will store fewer electrons and have a lower threshold voltage. For different memory cells 26, those which have xe2x80x9c0xe2x80x9d stored in them will not have the same threshold voltage, but will form a distribution like curve 30, more specifically they will have threshold voltages ranging from xe2x88x92V21 to xe2x88x92V22. Therefore, if a voltage between V11 and xe2x88x92V21 is inputted to every memory cell 26 of the flash memory 10, those with xe2x80x9c0xe2x80x9d stored in them will be turned on, and those with xe2x80x9c1xe2x80x9d will not be turned on. The binary data can be read according to the turn-on status through an external circuit, such as a sensing amplifier. Please note, the curves 28, 30 of the threshold voltage distribution are determined by the amount of electrical charge on the floating gate 18, which means the curves 28 and 30 show the positive threshold voltage distribution as well as the negative threshold voltage distribution.
In order to program and erase the flash memory 10, the amount of electrons stored on the floating gate 18 has to be controlled. To do so, methods such as Fowler-Nordheim tunneling or hot electron injection are usually used. Take Fowler-Nordheim tunneling for example, a control voltage Vcg of 10 volts is inputted to the control gate 20, a drain voltage Vd of 5 volts is applied to the drain 16, and a source voltage Vs of 0 volts is applied to the source 14. When electrons move from the source 14 to the drain 16 through the channel 22, an electrical field formed between the control gate 20 and the source 14 and an electrical field formed between the source 14 and the drain 16 pull the electrons towards the floating gate 18. While in hot electron injection, a potential difference between the source 14 and the drain 16 is applied at the same time a positive voltage is inputted to the control gate 20. The potential difference produces high energy electrons in the channel 22, and these high energy electrons further break electron bonding of surrounding atoms to give out more free electrons through an avalanche effect. Finally, the positive voltage at the control gate 20 draws the electrons in the channel 22 towards the floating gate 18.
Nevertheless, when compared to other memory devices, such as a dynamic random access memory (DRAM) with an access time of 1 ns, the charging and discharging of the floating gate 18 of the flash memory 10 is relatively quite slow and generally has an access time in the order of milliseconds. As mentioned above, when processing xe2x80x9creadxe2x80x9d commands, the flash memory 10 passes a voltage to the control gate 20 and determines the binary data stored by reading the correspondent output current or voltage. Since this does not involve the procedure of driving electrons to the floating gate 18, the flash memory 10 can read as fast as DRAM. However, when processing xe2x80x9cwritexe2x80x9d commands, the above procedure of driving electrons to the floating gate 18 is involved. This drags down the performance of the flash memory 10 and limits the application potential of a flash memory 10 in a rapid read-write environment. Nevertheless, for a conventional DRAM, data stored is volatile, so it is necessary for the DRAM to refresh periodically in order to retain the stored data. It is also expected that the stored data will be lost if the power is cut. Even though the conventional DRAM has an extremely high reading and writing speed, it is not able to store nonvolatile data without an external power supply.
It is therefore a primary objective of the claimed invention to provide a nonvolatile memory that has the function of volatile data storage to solve the above-mentioned problem.
According to the claimed invention, a nonvolatile memory comprises a plurality of memory cells, each of which having a substrate, a storage unit positioned on the substrate for storing data, a control unit positioned on the substrate, and a parasitic capacitor between the control unit and the storage unit. The storage unit comprises a floating gate for storing charges and a control gate for receiving an operational voltage to induce a conductive channel on the surface of the substrate. The storage unit is affected by establishment of the conductive channel. The conductive channel is related to a total number of charges stored on the floating gate.
According to the claimed invention, a control method applies a first predetermined voltage to the control unit, and then measures a voltage shift of the first predetermined voltage to determine data stored in the storage unit after the first predetermined voltage is passed through the parasitic capacitor.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.